The present invention relates to a process for preparing a semiconductor device with a narrow-channel MOS transistor, and more particularly to a method of forming a channel stopper by ion implantation.
In recent years, semiconductor devices show a tendency to make the capacity and integration increased, and with this, the devices have been promoted to be microminiaturized and to have multi-functions and variations. Under such circumstances, in a technical view point of manufacturing MOS transistors, a reduction of the channel length has been promoted for the former reason, or microminiaturizing whereas a lot of types of transistors which realize various functions have been developed for the latter or the multi functions.
Of these various MOS transistors, there is one type of the transistor which channel is small in width (so called as a narrow-channel transistor). The narrow-channel transistors have been prepared conventionally in the same manner as for preparing normal MOS transistors.
Now, the process for preparing a conventional narrow-channel transistor will be described with paying particular attention to the forming steps of preparing an oxide layer for element separation (field oxide layer) and a channel stopper in an n-MOS transistor.
In a step shown in FIG. 1A, there is provided, for example, a p-type silicon substrate 1 on which an oxide silicon layer 3 is formed, and an n-well 2 is selectively formed in the surface layer of the silicon substrate 1. In order to form an element separation insulating layer on the surface of the silicon substrate 1 provided with the selective n-well 2, silicon nitride film (an oxidation resistant film) 4 is formed on the entire surface. Thereafter, a first photo-resist film 5 is applied on the whole surface, then the first resist film 5 (5a, 5b and 5c) is selectively exposed using a resist mask for forming the element separation insulating layers. Subsequently the first resist film 5 is developed to remove the photo-resist film 5 from the places where the element separation insulating layer is to be formed. Thus the photo-resist film sections 5a, 5b and 5c are patterned. Then with the masking of the photo-resist film sections 5a, 5b and 5c, the plasma etching is effected to selectively remove the silicon nitride film 4 to form a pattern of oxidation resistant masking film made of the silicon nitride film 4.
Next, as shown in FIG. 1B, a second photo-resist film 6 is applied on the whole surface, then the film 6 is exposed with a mask for preparing a channel stopper. Then the exposed film is developed. With this process, there is made left a portion with the second photo-resist film 6 selectively above and in the vicinity of the n-well 2 alone. With the first photo-resist film sections 5a and 5b and the second photo-resist film 6 as the mask, a p-type impurity is ion-implanted onto the surface of the substrate 1 to selectively form a p-type ion implanted layer 7.
Subsequently, as shown in FIG. 1C and FIG. 2, after the first photo-resist film 5 (5a, 5b and 5c) and the second photo resist film 6 are removed, the surface of the substrate 1 masked by the silicon nitride film 4 is subjected to a thermal oxidation process. By this process, field oxide layers 8 (element separation insulating layers) are selectively formed on the surface of the substrate 1. Upon the thermal oxidation process, the impurity in the p-type ion implanted layer 7 are diffused to form a p-type channel stopper 9 under field oxide layer 8. After the completion of this process, the silicon nitride film 4 is removed.
In this manner stated above, there are provided a p-MOS transistor forming region 10, a n-MOS transistor forming region 11 and a narrow-channel MOS transistor forming region 12 each of which is separated by the field oxide layers 8. The procedure above is described in a case of the LOCOS method. In a case of the LOPOS method, the same procedure as in FIG. 1 is effected except that a step is added in which a polycrystalline silicon film is grown below the silicon nitride film.
FIG. 2 is a plan view corresponding to FIG. 1C. Here, a gate electrode 13 is referentially shown only for the narrow-channel n-MOS transistor by an alternate long and two short dashes line, and the region of the channel stopper 9 is shown by hatching.
Normally, the channel stopper 9 is shaped substantially similar to the field oxide layers 8. In some cases, however, as shown in FIG. 2, depending upon the conditions of the ion implantation and the thermal oxidation, the channel stopper 9 may be formed spreading into the n-MOS transistor forming region 11 and narrow-channel n-MOS transistor forming region 12.
However, in a case where a narrow-channel transistor is prepared by the conventional preparation process of a semiconductor device, the smallness of the channel width and the possible spreading of the channel stopper 9 due to various factors may cause the effective channel width to be decreased and substantially eliminated in the worst case.
The simplest solution of this problem is to set up a margin for the channel width of the narrow-channel MOS transistor forming region 12. In such case, there may be two methods, one of which is to evaluate a decrease of the channel width due to the channel stopper 9 and design the forming region 12 of the narrow-channel MOS transistor to be larger by taking a margin for making up for it. The other method is to design a transistor having as large a channel width as the decrease of the channel width does not cause any problem. In the first method, however, there is a difficulty that characteristics of the narrow-channel transistors vary widely due to the fluctuation of the process. On the other hand, the second method has a drawback that the occupying area of the narrow-channel transistor happens to be increased.